Field of the Invention
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to an apparatus and method for efficient register reclamation.
Description of the Related Art
Because the latency of accessing a register for reading/writing is usually less than one cycle, the register in a way is the fastest unit of the memory hierarchy. Typically, the “logical” registers, i.e., the registers exposed by the semantics of the instruction set architecture (ISA), are used by the compiler as sources/destinations for operands as well as for holding temporaries. However, prior to execution of this code on the hardware, the logical registers (LRegs) are mapped to a set of physical registers (PRegs) by a process called Register Allocation (RA).
Once the lifetime of the logical register is completed, i.e., there are no more consumers of the value held in the logical register prior to another value being stored in it, the logical-to-physical register mapping is torn down and the physical register is made available for allocation to another logical register. This process is called Register Reclamation (RR). Register mapping is typically held in a hardware table called the Register Allocation Table (RAT). The un-availability of free physical registers (i.e., physical registers not currently mapped to a logical register) causes all instruction allocation to stall until such a time that a free physical register is available, thereby reducing the performance.